用于时钟恢复电路的高速集成锁相环设计研究Design of a High-speed Integrated PLL for Clock Recovery Circuit
王小力,刘刚
摘要(Abstract)：
本文在0.25μm CMOS工艺下设计实现了一种可用于STM-16标准时钟恢复电路的锁相环模块.在理论分析基础上,分别采用Alexander结构、改进型电流舵开关技术、Maneatis环形振荡器结构设计了锁相环模块中的鉴相器(PD)、电荷泵和压控振荡器电路,并完成了整个锁相环模块的优化.经Hspice仿真实验,设计实现的锁相环中心频率为2.5 025 GHz,在3.3V电源电压下的功耗为40 mW,环路带宽为60 MHz,锁定时间约为640 ns,满足性能设计需求,并具有低功耗、低电源电压、低噪声等特点,研究结果对于光纤通信系统、FM解调器、立体声解调器、声音检测器、频率分析仪和其他很多应用都要重要价值.
关键词(KeyWords)： 时钟恢复电路;锁相环;鉴相器;电荷泵;压控振荡器
基金项目(Foundation): 教育部科学技术重点项目资助(03151)
作者(Author): 王小力,刘刚
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